1. Field of the Invention
The present invention relates to a storage device including a ferroelectric memory, a file storage device, and a computer system, and, more particularly, relates to an improvement of the data transfer capability of a ferroelectric memory and use of such a ferroelectric memory to realize a high speed, high reliability file storage device.
2. Description of the Related Art
In recent years, a variety of semiconductor memories using new memory materials have been proposed. Many of these memories enable high speed random access irrespective of being novolatile. Application in the future as “next generation memories” is promising.
As a representative example thereof, a ferroelectric memory can be explained. The cell structure and operation of the ferroelectric memory becoming the mainstream at present were proposed by S. Sheffield et al. in U.S. Pat. No. 4,873,664.
FIG. 1 is a circuit diagram showing an example of the configuration of the ferroelectric memory disclosed in U.S. Pat. No. 4,873,664, etc.
In this ferroelectric memory 10, a memory cell is configured by one access transistor 11 and one ferroelectric capacitor 12. Two values, that is, 1 bit, are stored according to a polarization direction of the ferroelectric capacitor. Further, in FIG. 1, BL11 and BL12 indicate bit lines, WL11 indicates a word line, PL11 indicates a plate line, 13 indicates a word line decoder and driver (WLDD), 14 indicates a plate line decoder and driver (PLDD), and 15 indicates a sense amplifier (SA).
For example, in the ferroelectric memory 10, when the word line WL11 is selected and, further, a pulse is applied to the plate line PL11, a read signal appears at the bit line BL11 connected to a facing electrode of the ferroelectric capacitor 12 of the memory cell.
This situation will be explained with reference to a hysteresis curve of FIG. 2. In FIG. 2, the abscissa indicates a voltage applied to the ferroelectric capacitor, and the ordinate indicates an amount of polarization.
In an initial state of reading, the plate line PL11 and the bit line BL11 are equalized to 0V, and the bit line BL11 becomes a floating state. The ferroelectric capacitor 12 is polarized in different directions according to the stored data. For example, with “0”, the state becomes “H0”, and with “1”, the state becomes (H1). Here, by applying a Vcc pulse to the plate line PL11, approximately Vcc is applied to both capacitors. Both of them shift to the state of (H2) together. Along with this, a signal difference corresponding to the difference of polarization displacements from the initial state appears at the bit line BL11 as a read signal difference of “0” and “1”.
Namely, only at the time when the “1” data is stored and the state is “H1”, the ferroelectric capacitor inverts in polarization, and a signal difference corresponding to the inversion appears at the bit line BL11. Specifically, the potential of the bit line BL11 becomes higher at the time of reading “1” with polarization inversion than that at the time of reading “0” without polarization inversion. Here, by supplying, for example, an intermediate potential of the “1” signal and the “0” signal as a reference signal and comparing the read signal and the reference signal by a differential type sense amplifier, it can be judged whether the above read signal is “1” or “0”. Further, the above ferroelectric memory sometimes stores 1 bit by using two memory cells complementarily storing the data. In such a format, complementary data are read out from the memory cells to a bit line pair connected to the sense amplifier, and the difference of these signals is judged at the sense amplifier by comparison. Accordingly, it is not necessary to separately generate the reference potential.
Note that, at the time of such a read operation, the data of the capacitor in the memory cell is destroyed once. Accordingly, at the time of the end of access, it is necessary to write back the data read out to the sense amplifier to the memory cell again. In this case, in a state where the signal amplified at the sense amplifier is transmitted to the bit line BL11, a pulse is applied to the plate line PL11 and a voltage is given between the facing electrodes of the capacitor 12 thereby to polarize the ferroelectric film again.
Further, Japanese Patent Publication (A) No. 2002-197857 and Japanese Patent Publication (A) No. 09-121032 or Japanese Patent Publication (A) No. 2002-197857 propose cross point type ferroelectric memories as a means for further improving the degree of integration of the above ferroelectric memory. These are the same as the ferroelectric memory described above in the point of storing two values by the polarization direction of the ferroelectric capacitor and selecting a memory cell selection by the word line and the plate line and therefore can be regarded as modifications of that memory.
The polarization inversion of such a ferroelectric capacitor can be executed at a high speed of about several nanoseconds. Accordingly, a ferroelectric memory can realize a random access speed near that of a SRAM or a DRAM irrespective of being nonvolatile.
FIG. 3 is a block diagram for explaining the access routine at a memory chip level of a ferroelectric memory.
A memory chip 20 of FIG. 3 includes a row decoder 21, an address register 22, a memory cell array 23, sense amplifiers 24, a column selector 25, and an input/output (I/O) buffer 26.
Basically the ferroelectric memory chip 20 is accessed according to the following three steps.
Step <1>
A word line and a plate line are selected from the row address, and the memory cell data is read out to the sense amplifiers.
Step <2>
The sense amplifiers are selected from the column address and the data is input/output.
Step <3>
The data is rewritten in the memory cells from the sense amplifiers.
This will be explained in further detail.
Step <1>
A row address among the addresses input from the outside and stored in the address register 22 is input to the row decoder 21, and a word line and a plate line are selected from the memory cell array 23. 16 words (256 bits) worth of data selected from this combination and read out as explained above are decided on and latched at the sense amplifiers 24.
Step <2>
A column address among the addresses stored in the address register 22 is input to the column selector 25, and 1 word (16 bits) of corresponding sense amplifiers are selected from the sense amplifiers 24. At the time of a read operation, the data of the sense amplifiers is output via the I/O buffer 26, while at the time of a write operation, the data of the sense amplifiers is updated to the data input from the outside via the I/O buffer 26.
Step <3>
The data of the sense amplifiers 24 is written back into the read memory cells selected at step <1>.
Usually, about 5 nanoseconds are necessary in order to sufficiently judge polarization of a ferroelectric capacitor. Further, when considering the input of an address and decoding thereof, a cell array operation and sensing, the transfer of internal data, the drive of an external load by the buffer at the time of the data output, and so on, for example, 35 nanoseconds become necessary for step <1>, 15 nanoseconds become necessary for the output of step <2>, and about 15 nanoseconds become necessary for step <3>. After passing about 65 nanoseconds, the random access with respect to 1 word of the memory chip 20 is completed.
Further, in the case of a ferroelectric memory, the ferroelectric film is polycrystalline, and therefore the polarization characteristic varies quite a bit. As a technique for substantially reducing the influence of such variations and improving the operating margin, an introduction of an error correction code (ECC) is effective.
When correcting error inside the chip, in order to decrease the relative number of parity bits, often a plurality of words are used as units, for example, units of 32 bits. In that case, it is necessary to serially execute the decoding and the encoding of the data in the above step <2>. Accordingly, the time taken by step <2> becomes further longer.
FIG. 4 is a block diagram for explaining the access routine at the memory chip level of a ferroelectric memory introducing error correction code (ECC).
A memory chip 20A of FIG. 4 includes the row decoder 21, the address register 22, the memory cell array 23, the sense amplifiers 24, the column selector 25, and the input/output (I/O) buffer 26 of FIG. 3 plus a second column selector 27, an I/O register 28, an ECC decoder 29, and an ECC encoder 30.
The ferroelectric memory chip 20A of FIG. 4 is accessed by the following three steps. Note that the operations of step <1> and step <3> are the same as in the case of FIG. 3.
Step <1>
A row address among the addresses input from the outside and stored in the address register 22 is input to the row decoder 21, and a word line and a plate line are selected from the memory cell array 23. 16 words (256 bits+42 bits) worth of data of the memory cells selected from this combination and read out as explained above are decided on and latched at the sense amplifiers 24.
Step <2>
The higher bits of the column address among the addresses stored in the address register 22 are input to the column selector 25 and decoded, and 2 words' worth (32+6 bits) of corresponding sense amplifiers are selected from the sense amplifiers 24. The data is decoded at the ECC decoder 29, corrected for error, and then latched at the I/O register 28. Further, the lower bits of the column address are input to the column selector 27, and 1 word (16 bits) is selected from the register 28. At the time of a read operation, that value is output via the I/O buffer 26. On the other hand, at the time of a write operation, that value is rewritten, further encoded at the ECC encoder 30, and written back to the original locations of the sense amplifiers 24.
Step <3>
The data of the sense amplifiers 24 is written back to the read memory cells selected at step <1>.
In the above case, for step <2>, the processing of encoding or decoding is serially added. Further, for at least the write operation, the work of rewriting a portion of data once read out from the sense amplifiers 24 and further writing back the same into the sense amplifiers 24 becomes necessary. Due to this, for step <2>, a time of 5 nanoseconds to 10 nanoseconds is further taken.
Accordingly, after approximately 70 to 75 nanoseconds for steps <1> to <3>, random access with respect to one word of the memory chip 20A is completed.